`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:42:00 11/01/2008 
// Design Name: 
// Module Name:    ConditionTable 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ConditionTable(
    input [3:0] CondCode,
	 input [15:0] flag,          
    output reg result	 
    );
								
   //From Most significant to least significant bit
	//  these are C, L, F, Z, N
	wire [4:0] PSRCodes = {flag[15],flag[13],flag[10],flag[9],flag[8]};

	// The following always block is a copy of Table 1 in the ISA
	// CondCode = extended opcode
	always@(CondCode) begin 					// Since the only instructions that use
		case (CondCode)							// this are Bcond and Jcond we can assume
			4'b0000: result<=PSRCodes[1];		// that the PSR codes have all settled
			4'b0001: result<=~PSRCodes[1];	// down and are correct
			4'b1101: result<=(PSRCodes[0]|PSRCodes[1]);
			4'b0010: result<=PSRCodes[4];
			4'b0011: result<=~PSRCodes[4];
			4'b0100: result<=PSRCodes[3];
			4'b0101: result<=~PSRCodes[3];
			4'b1010: result<=(~PSRCodes[3]&~PSRCodes[1]);
			4'b1011: result<=(PSRCodes[3]|PSRCodes[1]);
			4'b0110: result<=PSRCodes[0];
			4'b0111: result<=~PSRCodes[0];
			4'b1000: result<=PSRCodes[2];
			4'b1001: result<=~PSRCodes[2];
			4'b1100: result<=(~PSRCodes[0]&~PSRCodes[1]);
			4'b1110: result<=1;
			4'b1111: result<=0;
			default: result<=0;
		endcase
	end
endmodule
